Optimization Of a Keccak Hardware Accelerator Protected Against Side-Channel Attacks H/F - CEA

Le CEA est un acteur majeur de la recherche, au service des citoyens, de l'économie et de l'Etat.

Il apporte des solutions concrètes à leurs besoins dans quatre domaines principaux : transition énergétique, transition numérique, technologies pour la médecine du futur, défense et sécurité sur un socle de recherche fondamentale. Le CEA s'engage depuis plus de 75 ans au service de la souveraineté scientifique, technologique et industrielle de la France et de l'Europe pour un présent et un avenir mieux maîtrisés et plus sûrs.

Implanté au coeur des territoires équipés de très grandes infrastructures de recherche, le CEA dispose d'un large éventail de partenaires académiques et industriels en France, en Europe et à l'international.

Les 20 000 collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales :

- La conscience des responsabilités
- La coopération
- La curiositéThe objective of this internship is to optimize a first-order masked Keccak accelerator implementing Domain Oriented Masking (DOM) for protection against side-channel attacks. The work focuses on reducing both the hardware area and the amount of randomness required by the countermeasure, without compromising security. Starting from the existing masked SHA-3 accelerator developed at CEA [1], the student will analyze the main sources of area overhead introduced by the masking and randomness generation mechanisms. Based on this analysis, alternative micro-architectural solutions for the non-linear Keccak steps and the randomness dispatcher will be investigated to improve efficiency. The optimized design will be modeled in HDL and synthesized on FPGA or ASIC targets to evaluate cost, performance, and scalability. Security validation will be conducted using Test Vector Leakage Assessment (TVLA). The expected outcome is a more compact and resource-efficient masked Keccak accelerator that maintains first-order resistance, enabling practical deployment of secure SHA-3 hardware in post-quantum cryptographic systems.

This offer is dedicated to master students looking for an ambitious research-oriented internship. If you are looking for an experience in ASIC and FPGA design with industrial-grade tools and processes, this internship is perfect for you! It is required to have graduate-level experience in FPGA and ASIC design and be familiar with arithmetic circuit microarchitectures, RTL modelling (VHDL or Verilog/SystemVerilog) and synthesis (Synopsys Design Compiler, Xilinx Vivado).